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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12514-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89670/A Series
MB89673/677A/P677A/PV670A
s DESCRIPTION
The MB89670/A series has been developed as a line of proprietary 8-bit, single-chip microcontrollers. In addition to the F2MC*-8L CPU core which can operate at low voltage but at high speed, the microcontrollers contain pheripheral functions such as timers, a serial interface, an A/D converter, a UART, an up/down counter, and an external interrupt. The MB89670/A series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.
Instruction set optimized for controllers
* High-speed processing at low voltage * Minimum execution time: 0.4 s/3.5 V, 0.8 s/2.7 V, 2.0 s/2.2 V * I/O ports: max. 69 channels
(Continued)
s PACKAGE
80-pin Plastic QFP 80-pin Plastic QFP 80-pin Ceramic MQFP
(FPT-80P-M11)
(FPT-80P-M06)
(MQP-80C-P01)
MB89670/A Series
(Continued) * Timers: 9 channels (MB89670A: 12 channels) 8-bit PWM timer: 3 channels (MB89670A: 6 channels) (also usable as a reload timer) 16-bit timer/counter 21-bit time-base timer 8/16-bit timer (8 bits x 2 channels or 16 bits) 8/16-bit up/down counter timer (8 bits x 2 channels or 16 bits) * Two serial interfaces 8-bit synchronized serial: 1 channel (Switchable transfer direction allows communication with various equipment.) UART: 1 channel (with full-duplex double buffer) * External interrupts: 8 channels Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). * Buzzer output * 10-bit A/D converter 8-channel input * Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) * Bus interface function Including hold and ready functions
2
MB89670/A Series
s PRODUCT LINEUP
Part number Parameter
MB89673*1
MB89677A
MB89P677A
MB89PV670A
Classification ROM size RAM size CPU functions
Mass production products (mask ROM products) 8 K x 8 bits (internal mask ROM) 384 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Output ports (N-channel open-drain): Output ports (CMOS): I/O ports (N-channels open-drain): I/O ports (CMOS): Input ports: Total: Specify when ordering masking 32 K x 8 bits (internal mask ROM)
One-time PROM product Piggyback/ evaluation product (for development) (for development)
32 K x 8 bits (internal PROM) 1 K x 8 bits
48 K x 8 bits (external ROM)
136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 s/10 MHz to 6.4 s/10 MHz 3.6 s/10 MHz to 57.6 s/10 MHz 14 (12 also serve as peripherals.) 8 (All also serve as peripherals.) 7 (All also serve as peripherals.) 32 (All also serve as peripherals.) 8 (All also serve as peripherals.) 69 Set with EPROM programmer Setting not possible
Ports
Option 21-bit timebase timer 8/16-bit up/ down counter
21 bits (0.81 ms, 3.27 ms, 26.21 ms, 419 ms/10 MHz) 8 bits x 2 channels or 16 bits x 1 channel Timer operation Up/down counter operation Phase difference counting (successive double mode, quadruple mode) 16-bit timer operation 16-bit event counter operation (edge selectability) 8 bits x 2 channels or 16 bits x 1 channel Reload timer operation (toggled output capable) Event counter operation 8 bits x 2 channels reload timer operation (toggled output capable) 8 bits x 2 channels PWM operation (four fixed frequency) 8 bits x 1 channel PPG operation (variable frequency) Capable of output switching between 2 channels 8-bit reload timer operation (toggled output capable) 8-bit PWM operation (four fixed frequency) Capable of output switching between 2 channels 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks)
16-bit timer/ counter 8/16-bit timer counter 8-bit PWM timer 1, 8-bit PWM timer 2 8-bit PWM timer 3, 8-bit PWM timer 4, 5, 6 8-bit serial I/O
(Continued)
3
MB89670/A Series
(Continued)
Part number Parameter
MB89673*1
MB89677A
MB89P677A
MB89PV670A
UART
Variable data length (7 or 8 bits) Internal baud rate generator Error detection function Intenal full-duplex double buffer NRZ transfer format CLK synchrnous/asynchronous data transfer capable 10 bit x 8 channels 8 channels (Rising edge/falling edge) 2.2 V to 6.0 V 2.7 V to 6.0 V MBM27C512-20TV (LCC package)
10-bit A/D converter External interrupt Operating voltage*2 EPROM for use
*1: 8-bit PWM timer 4, 5, and 6 is not provided for the MB89673. *2: The minimum operating voltage varies with the operating frequency, the function, and the connected ICE.
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-80P-M06 FPT-80P-M11 MQP-80C-P01 : Available x MB89673 MB89677A MB89P677A MB89PV670A x x*
x : Not available
* : Lead pitch converter sockets (manufacturer: Sun Hayato Co., Ltd.) are available 80QF-80QF2-8L-UP + (MQP-80C-P01 or FPT-80P-M06) for conversion to FPT-80P-M11 80QF-80QF2-8L-DWN Note: For more information about each package, see section "s Package Dimensions."
4
MB89670/A Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * On the MB89P677A, the program area starts from address 8007H but on the MB89677A and MB89PV670A starts from 8000H. (On the MB89P677A, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89677A and MB89PV670A, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P677A.) * The stack area, etc., is set at the upper limit of the RAM. * The external area is used.
2. Current Consumption
* In the case of the MB89PV670A, add the current consumed by the EPROM which is connected to the top socket. * When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections "s Electrical Characteristics" and "s Example Characteristics.")
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s Mask Options." Take particular care on the following point: * Options are fixed on the MB89PV670A.
s CORRESPONDENCE BETWEEN THE MB89670/A AND MB89670R/AR SERIES
* The MB89670R/AR series is the reduction version of the MB89670/A series. For their differences, refer to the MB89670R/AR series data sheet. MB89670/A series MB89670R/AR series MB89673 MB89673R -- MB89675R MB89677A MB89677AR
MB89P677A
MB89PV670A
5
MB89670/A Series
s PIN ASSIGNMENT
(Top view) P74/SCK P75/SO P76/SI AVSS AVR AVCC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/INT0/ADST P61/INT1 P62/INT2 P63/INT3 P64/INT4 P65/INT5 P73/UI P72/UO P71/UCK P70/BZ1 P83 P82 P81 P80 MOD0 MOD1 X0 X1 VSS RST P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P66/INT6 P67/INT7 P84 P85 VSS P40/PWM00 P41/PWM01 VCC P42/PWM10/BZ2 P43/PWM11 P44/TCI P45/TCO1 P46/TCO2 P47/EC P30/PWM20 P31/PWM21 P32/UDZ1 P33/UDB1 P34/UDA1 P35/UDZ2
6
P21/HAK P20/BUFC P17/A15 P16/A14 P15/A13 P14/A12 P13/A11 P12/A10 P11/A09 P10/A08 P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P37/UDA2 P36/UDB2 (FPT-80P-M11)
MB89670/A Series
(Top view) P76/SI AVSS AVR AVCC P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/INT0/ADST P61/INT1 P62/INT2 P63/INT3 P75/SO P74/SCK P73/UI P72/UO P71/UCK P70/BZ1 P83 P82 P81 P80 MOD0 MOD1 X0 X1 VSS RST P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
101 102 103 104 105 106 107 108 109
93 92 91 90 89 88 87 86 85
Each pin inside the dashed line is for the MB89PV670A only.
P64/INT4 P65/INT5 P66/INT6 P67/INT7 P84 P85 VSS P40/PWM00 P41/PWM01 VCC P42/PWM10/BZ2 P43/PWM11 P44/TCI P45/TCO1 P46/TCO2 P47/EC P30/PWM20 P31/PWM21 P32/UDZ1 P33/UDB1 P34/UDA1 P35/UDZ2 P36/UDB2 P37/UDA2
* Pin assignment on package top (MB89PV670A only) Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. A15 A12 A7 A6 A5 A4 A3 Pin no. 89 90 91 92 93 94 95 96 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 97 98 99 100 101 102 103 104 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 105 106 107 108 109 110 111 112 Pin name OE/VPP N.C. A11 A9 A8 A13 A14 VCC
N.C.: Internally connected. Do not use. 7
P17/A15 P16/A14 P15/A13 P14/A12 P13/A11 P12/A10 P11/A09 P10/A08 P07/AD7 P06/AD6 P05/AD5 P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 (FPT-80P-M06) (MQP-80C-P01)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
110 111 112 81 82 83 84
100 99 98 97 96 95 94
MB89670/A Series
s PIN DESCRIPTION
Pin no. QFP*1 11 12 9 10 14 QFP*2 MQFP*3 13 14 11 12 16 X0 X1 MOD0 MOD1 RST C B Operating mode selection pins Connect directly to VCC or VSS. Reset I/O pin This pin is an N-ch open-drain output type with pull-up resistor and a hysteresis input. "L" is output from this pin by an internal reset source. The internal circuit is initialized by the input of "L". General-purpose I/O ports When an external bus is used, these ports function as multiplex pins of lower address output and data I/O. General-purpose I/O ports When an external bus is used, these ports function as upper address output pins. F General-purpose output port When an external bus is used, this port can also be used as a buffer control output by setting the BCTR. General-purpose output port When an external bus is used, this port can also be used as a hold acknowledge output by setting the BCTR. General-purpose output port When an external bus is used, this port can also be used as a hold request input by setting the BCTR. General-purpose output port When an external bus is used, this port functions as a ready input. General-purpose output port When an external bus is used, this port functions as a clock output. General-purpose output port When an external bus is used, this port functions as a write signal output. General-purpose output port When an external bus is used, this port functions as a read signal output. General-purpose output port When an external bus is used, this port functions as an address latch signal output. Pin name Circuit type A Clock oscillator pins Function
38 to 31
40 to 33
P00/AD0 to P07/AD7 P10/A08 to P17/A15 P20/BUFC
D
30 to 23
32 to 25
22
24
21
23
P21/HAK
F
20
22
P22/HRQ
D
19
21
P23/RDY
D
18
20
P24/CLK
F
17
19
P25/WR
F
16
18
P26/RD
F
15
17
P27/ALE
F
*1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01
(Continued)
8
MB89670/A Series
Pin no. QFP*1 46 QFP*2 MQFP*3 48 Pin name P30/PWM20
Circuit type D
Function General-purpose I/O port Also serves as the PWM20 output for the 8-bit PWM timer. General-purpose I/O port Also serves as the PWM21 output for the 8-bit PWM timer. General-purpose I/O port Also serves as the Z-phase input for the 16-bit up/down counter/timer. General-purpose I/O port Also serves as the B-phase input for the 16-bit timer/ counter. General-purpose I/O ports Also serves as the A-phase input for the 16-bit up/down counter/timer. General-purpose I/O port Also serves as the Z-phase input for the 16-bit up/down counter/timer. General-purpose I/O port Also serves as the B-phase input for the 16-bit up/down counter/timer. General-purpose I/O port Also serves as the A-phase input for the 16-bit up/down counter/timer. General-purpose I/O port Also serves as the PWM00 output for the 8-bit PWM timer. General-purpose I/O port Also serves as the PWM01 output for the 8-bit PWM timer. General-purpose I/O port Also serves as the PWM10 and the BZ2 output for the 8bit PWM timer. General-purpose I/O port Also serves as the PWM11 output for the 8-bit PWM timer. General-purpose I/O port Also serves as the TCI input for the 8/16-bit timer/ counter. General-purpose I/O port Also serves as the TCO1 output for the 8/16-bit timer/ counter.
45
47
P31/PWM21
D
44
46
P32/UDZ1
E
43
45
P33/UDB1
E
42
44
P34/UDA1
E
41
43
P35/UDZ2
E
40
42
P36/UDB2
E
39
41
P37/UDA2
E
55
57
P40/PWM00
D
54
56
P41/PWM01
D
52
54
P42/PWM10/ BZ2 P43/PWM11
D
51
53
D
50
52
P44/TCI
E
49
51
P45/TCO1
D
*1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01
(Continued)
9
MB89670/A Series
(Continued)
Pin no. QFP*1 48 QFP*2 MQFP*3 50 Pin name P46/TCO2 Circuit type D Function General-purpose I/O port Also serves as the TCO2 output for the 8/16-bit timer/ counter. General-purpose I/O port Also serves as input for the16-bit timer/counter. The EC input is a hysteresis input type. N-ch open-drain output ports Also serve as the analog input for the A/D converter. General-purpose input port The software pull-up resistor is provided. Also serves as an external interrupt input (INT0) and an A/D converter external activation. This port is a hysteresis input type. General-purpose input ports A software pull-up resistor is provided. Also serve as an external interrupt input (INT1 to INT7). These ports are a hysteresis input type. N-ch open-drain I/O port Also serves as a buzzer output. N-ch open-drain I/O port Also serves as a UART clock I/O (UCK) switchable to CMOS. N-ch open-drain I/O port Also serves as a UART data output (UO) switchable to CMOS. N-ch open-drain I/O port Also serves as a UART data input (UI). N-ch open-drain I/O port Also serves as the clock I/O for the serial I/O (SCK) switchable to CMOS. N-ch open-drain I/O port Also serves as the data output (SO) for the serial I/O switchable to CMOS. N-ch open-drain I/O port Also serves as the data input (SI) for the serial I/O. N-ch open-drain output ports
47
49
P47/EC
E
74 to 67 66
76 to 69 68
P50/AN0 to P57/AN7 P60/INT0/ ADST
I J
65 to 59
67 to 61
P61/INT1 to P67/INT7
J
4 3
6 5
P70/BZ1 P71/UCK
G K
2
4
P72/UO
K
1 80
3 2
P73/UI P74/SCK
G K
79
1
P75/SO
K
78 8 to 5 57, 58 53 13, 56 75 76 77
80 10 to 7 59, 60 55 15, 58 77 78 79
P76/SI P80 to P83 P85, P84 VCC VSS AVCC AVR AVSS
G H
-- -- -- -- --
Power supply pin Power supply (GND) pin A/D converter power supply pin A/D converter reference voltage input pin A/D converter power supply pin Use this pin at the same voltage as VSS.
*1: FPT-80P-M11 *2: FPT-80P-M06 *3: MQP-80C-P01 10
MB89670/A Series
* External EPROM pins (MB89PV670A only) Pin no. 82 83 84 85 86 87 88 89 90 91 93 94 95 96 98 99 100 101 102 103 104 105 107 108 109 110 111 112 81 92 97 106 Pin name A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE/VPP A11 A9 A8 A13 A14 VCC N.C. I/O O Address output pins Function
I
Data input pins
O I
Power supply (GND) pin Data input pins
O O O O
ROM chip enable pin Outputs "H" during standby. Address output pin ROM output enable pin Outputs "L" at all times. Address output pins
O O O -- Internally connected pins Be sure to leave them open.
11
MB89670/A Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks Crystal or ceramic oscillation type * At an oscillation feedback resistor of approximately 1 M/5.0 V
X0
Standby control signal
B
C
R P-ch
* At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * Hysteresis input
N-ch
D
R P-ch P-ch
* CMOS output * CMOS inout
N-ch
* Pull-up resistor optional (except P22 and P23) E
R P-ch P-ch
* CMOS output * CMOS input * The peripheral is a hysteresis input type.
N-ch Peripheral
Port
* Pull-up resistor optional
(Continued)
12
MB89670/A Series
(Continued)
Type F
P-ch
Circuit * CMOS output
Remarks
N-ch
G
R P-ch
* N-ch open-drain output * Hysteresis input
P-ch
N-ch
* Pull-up resistor optional H
N-ch
* N-ch open-drain output
I
P-ch
* N-ch open-drain output * Analog input
N-ch
Analog input
J
R P-ch Pull-up control signal
* Hysteresis input * With software pull-up resistor
K
R P-ch P-ch
* CMOS output * Hysteresis input
N-ch
* Pull-up resistor optional 13
MB89670/A Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
14
MB89670/A Series
s PROGRAMMING TO THE EPROM ON THE MB89P677A
The MB89P677A is an OTPROM version of the MB89670/A series.
1. Features
* 32-Kbyte PROM on chip * Options can be set using the EPROM programmer. * Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
Normal operating mode 0000H I/O 0080H 0100H 0200H Register RAM
EPROM mode (Corresponding addresses on the EPROM programmer)
0480H External area 8000H Option area 8007H 0007H 0000H Option area
PROM
Program area (EPROM)
FFFFH
7FFFH
15
MB89670/A Series
3. Programming to the EPROM
In EPROM mode, the MB89P677A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as a normal operating mode assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see "7. Bit Map for PROM Options.") (3) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package FPT-80P-M11 FPT-80P-M06 Compatible socket adapter ROM-80QF2-28DP-8L ROM-80QF-28DP-8L2
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 F between VPP and VSS or VCC and VSS can stabilize programming operations.
16
MB89670/A Series
7. PROM Option Bit Map
The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: Bit 7 Vacancy
0000H
Bit 6 Vacancy Readable P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes Vacancy Readable Vacancy Readable Vacancy Readable
Bit 5 Vacancy Readable P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes Vacancy Readable Vacancy Readable Vacancy Readable
Bit 4 Vacancy Readable P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes Vacancy Readable P74 Pull-up 1: No 0: Yes Vacancy Readable
Bit 3 Reset pin output 1: Yes 0: No P13 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes Vacancy Readable P73 Pull-up 1: No 0: Yes P04 to P07 Pull-up 1: No 0: Yes
Bit 2 Power-on reset 1: Yes 0: No P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes Vacancy Readable P72 Pull-up 1: No 0: Yes P00 to P03 Pull-up 1: No 0: Yes
Bit 1 00: 24/FC 10: 217/FC P11 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes Vacancy Readable P71 Pull-up 1: No 0: Yes P76 Pull-up 1: No 0: Yes
Bit 0 01: 214/FC 11: 218/FC P10 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes Vacancy Readable P70 Pull-up 1: No 0: Yes P75 Pull-up 1: No 0: Yes
Oscillation stabilization time
Readable P17 Pull-up 1: No 0: Yes P37 Pull-up 1: No 0: Yes P47 Pull-up 1: No 0: Yes Vacancy
0001H
0002H
0003H
0004H
Readable Vacancy
0005H
Readable Vacancy
0006H
Readable
Notes: * Set each bit to 1 to erase. * Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it.
17
MB89670/A Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32(Rectangle) Adapter socket part number ROM-32LC-28DP-YG
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode is diagrammed below.
Address 0000H
Normal operating mode
Corresponding address on the EPROM programmer 0000H
I/O 0080H RAM 0480H External area 4000H 4000H Not available
8000H * 8007H
8000H * 8007H
PROM 48 KB
EPROM 48 KB
FFFFH
FFFFH
*: Note that for the MB89P677A this area comprise an option setting area.
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 4000H to FFFFH. (3) Program to 4000H to FFFFH with the EPROM programmer.
18
MB89670/A Series
s BLOCK DIAGRAM
1. MB89673
X0 X1
Oscillator
Time-base timer
Clock controller
CMOS I/O port
RST
Reset circuit (WDT)
Internal bus
16-bit up/down counter 8-bit up/down counter P37/UDA2 P36/UDB2 P35/UDZ2 P34/UDA1 P33/UDB1 P32/UDZ1
RAM
8-bit up/down counter
F2MC-8L CPU 16-bit timer/counter ROM 8/16-bit timer CMOS I/O port 8 P00/AD0 to P07/AD7 8 P10/A08 to P17/A15 MOD0 MOD1 P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC 6 P80 to P85 8 External bus interface 8-bit timer 8-bit timer P46/TCO2 P45/TCO1 P44/TCI P47/EC
2-channel 8-bit PWM timer 8-bit timer #2 8-bit timer #1 P43/PWM11 P42/PWM10/BZ2 P41/PWM01 P40/PWM00
P31/PWM21 8-bit PWM timer #3 P30/PWM20 CMOS output port N-ch open-drain output port 8 10-bit A/D converter UART P73/UI P72/UO P71/UCK 8-bit serial P76/SI P75/SO P74/SCK
P50/AN0 to P57/AN7 AVR AVCC AVSS
Buzzer output Input port P60/INT0/ADST to P67/INT7 8 8 External interrupt N-ch open-drain I/O port
P70/BZ1
19
MB89670/A Series
2. MB89677A/89P677A/89PV670A
X0 X1
Time-base timer Oscillator CMOS I/O port Clock controller 16-bit up/down counter
RST
Internal bus
Reset circuit (WDT)
8-bit up/down counter
P37/UDA2 P36/UDB2 P35/UDZ2 P34/UDA1 P33/UDB1 P32/UDZ1
RAM
8-bit up/down counter
F2MC-8L CPU
16-bit timer/counter
P47/EC
8/16-bit timer ROM 8-bit timer CMOS I/O port 8 P00/AD0 to P07/AD7 8 P10/A08 to P17/A15 MOD0 MOD1 P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC
6
P46/TCO2 P45/TCO1 P44/TCI
8-bit timer
8-bit PWM timer #3
P30/PWM20
8-bit PWM timer #4
P31/PWM21
External bus interface
8-bit PWM timer #5
P41/PWM01
8-bit PWM timer #6 2-channel 8-bit PWM timer 8-bit timer #1 CMOS output port N-ch open-drain output port
8
P43/PWM11
8-bit timer #2
P40/PWM00 P42/PWM10/BZ2
P80 to P85
8
8-bit serial
P76/SI P75/SO P74/SCK
P50/AN0 to P57/AN7 AVR AVCC AVSS
10-bit AD converter UART
P73/UI P72/UO P71/UCK
Input port Buzzer output P60/INT0/ADST to P67/INT7
8 8
P70/BZ1
External interrupt N-ch open-drain I/O port
20
MB89670/A Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89670/A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89670/A series is structured as illustrated below. Memory Space
MB89673 MB89P677A MB89677A 0000H I/O RAM Register 0200H 0200H 0080H 0100H I/O RAM Register 0200H 0000H 0080H 0100H I/O RAM Register MB89PV670A
0000H 0080H 0100H
0480H External area External area
0480H External area 4000H
8000H * 8007H
8000H
Option PROM (One-time PROM product)*
8000H * 8007H
8007H
E000H ROM FFFFH FFFFH
Programmable ROM
Programmable ROM
FFFFH
*: Since addresses 8000H to 8006H for the MB89P677A comprise an option area, do not use this area for the other products in this series.
21
MB89670/A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided:
Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS):
A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15 PS
14
13 RP
12
11
10
9
8
7 H
6 I
5
4
3 N
2 Z
1 V
0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
22
MB89670/A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit.
IL1 0 0 1 1
IL0 0 1 0 1
Interrupt level 1 2 3
High-low High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction.
23
MB89670/A Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89677A. On the MB89673, there are 16 banks in internal RAM. The remaining 16 banks can be extended externally by allocating an external RAM to addresses 0180H to 01FFH using an external circuit. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
24
MB89670/A Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) SMR SDR (R/W) (W) (R/W) (W) (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) PDR3 DDR3 PDR4 DDR4 PDR5 PDR6 PPCR PDR7 PDR8 BUZR CNTR COMP TMCR TCHR TCLR (R/W) (R/W) (R/W) (R/W) SYCC STBC WDTE TBCR Read/write (R/W) (W) (R/W) (W) (R/W) (W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 BCTR Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register External bus pin control register Vacancy System clock control register Standby control register Watchdog timer control register Time-base timer control register Vacancy Port 3 data register Port 3 data direction register Port 4 data register Port 4 data direction register Port 5 data register Port 6 data register Port 6 pull-up control register Port 7 data register Port 8 data/port 7 swiching register Buzzer control register PWM control register #3 PWM compare register #3 16-bit timer control register 16-bit timer count register H 16-bit timer count register L Vacancy Serial mode register Serial data register Vacancy Vacancy 0000 XXXX 0000B XXXXB XXXX 0000 XXXX 0000 1111 XXXX 0000 X1 1 1 0011 XXXX 0000 XXXX 0000 0000 0000 XXXXB 0000B XXXXB 0000B 1111B XXXXB 0000B 1111B 1111B X0 0 0 B 0000B XXXXB 0000B 0000B 0000B X - - M MX 0 0 B 0001 XXXX 0 0 XX XXXXB XXXXB X0 0 0 B Initial value XXXX 0000 XXXX 0000 0000 XXXX XXXXB 0000B XXXXB 0000B 0000B XX0 1 B
-: Unused, X: Undefined, M: Set using the mask option
(Continued)
25
MB89670/A Series
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (W)
Register name ADC1 ADC2 ADCH ADCL T2CR T1CR T2DR T1DR CNTR1 CNTR2 CNTR3 COMR2 COMR1
Register description A/D converter control register 1 A/D converter control register 2 A/D converter data register H A/D converter data register L Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register PWM timer control register 1 PWM timer control register 2 PWM timer control register 3 PWM timer compare register 2 PWM timer compare register 1 Vacancy Vacancy Vacancy
Initial value 0000 X0 0 0 ---- XXXX X0 0 0 X0 0 0 XXXX XXXX 0000 0000 XXX0 XXXX XXXX 0000B 0001B - - XXB XXXXB XXX0 B XXX0 B XXXXB XXXXB 0000B 0000B 0000B XXXXB XXXXB
(R) (W) (R) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
UDCR1 RCR1 UDCR2 RCR2 CCRA1 CCRA2 CCRB1 CCRB2 CSR1 CSR2 EIC1 EIC2 EIE2 EIF2
Up/down counter register 1 Reload compare register1 Up/down counter register 2 Reload compare register2 Counter control register A1 Counter control register A2 Counter control register B1 Counter control register B2 Counter status register 1 Counter status register 2 External interrupt 1 control register 1 External interrupt 1 control register 2 External interrupt 2 enable register External interrupt 2 flag register Vacancy Vacancy Vacancy Vacancy
XXXX XXXX XXXX XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX
XXXXB XXXXB XXXXB XXXXB 0000B 0000B 0000B 0000B 0000B 0000B 0000B 0000B 0000B 0000B
-: Unused, X: Undefined, M: Set using the mask option
(Continued)
26
MB89670/A Series
(Continued)
Address 40H 41H 42H 43H 44H 45H 46H 47H 48H* 49H* 4AH* 4BH* 4CH* 4DH* 4E to 7AH 7BH 7CH 7DH 7EH 7FH (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) CNTR #4 COMP #4 CNTR #5 COMP #5 CNTR #6 COMP #6 (R/W) RRDR Read/write (R/W) (R/W) (R/W) (R) (W) Register name USMR USCR USTR RXDR TXDR Register description UART mode register UART control register UART status register UART receiver data register UART transmitter data register Vacancy Baud rate generator reload data register Vacancy Vacancy PWM timer control register #4 PWM timer compare register #4 PWM timer control register #5 PWM timer compare register #5 PWM timer control register #6 PWM timer compare register #6 Vacancy Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy 1111 1111 1111 1111B 1111B 1111B 0 X0 0 XXXX 0 X0 0 XXXX 0 X0 0 XXXX 0000B XXXXB 0000B XXXXB 0000B XXXXB XXXX XXXXB Initial value 0000 0000 0000 XXXX XXXX 0000B 0000B 1 XXXB XXXXB XXXXB
-: Unused, X: Undefined, M: Set using the mask option * : For the MB89673, these are vacancies. Note: Do not use vacancies.
27
MB89670/A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter Power supply voltage A/D converter reference input voltage Input voltage Output voltage "L" level maximum output current
Symbol VCC AVCC AVR VI VO1 VO2 IOL IOLAV1
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- -- -40 -55 Max. VSS + 7.0 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VSS + 7.0 20 4 8 100 40 -20 -4 -50 -20 300 +85 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mA mW C C *
Remarks
AVR must not exceed AVCC + 0.3 V.
Except P80 to P85 P80 to P85
Average value (operating current x operating rate) Average value (operating current x operating rate) P80 to P85
"L" level average output current IOLAV2 "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
Average value (operating current x operating rate)
Average value (operating current x operating rate)
Average value (operating current x operating rate)
* : Use AVCC and VCC set at the same voltage. Take care so that AVR does not exceed AVCC + 0.3 V and AVCC does not exceed VCC, such as when power is turned on. Precautions: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
28
MB89670/A Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value Min. 2.2* Max. 6.0 6.0 6.0 AVCC +85
Unit V V V V C
Remarks Normal operation assurance range MB89673/677A Normal operation assurance range MB89PV670A/P677A Retains the RAM state in stop mode
Power supply voltage
VCC
2.7* 1.5
A/D converter reference input voltage Operating temperature
AVR TA
0.0 -40
* : These values vary with the operating frequency, and analog assurance range. See Figure 1 and "5. A/D Converter Electrical Characteristics."
6
5 Operation assurance range Operating voltage (V) 4 A/D converter accuracy assured in the VCC = AVCC = 3.5 V to 6.0 V range.
3
2
1
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Clock operating frequency (MHz)
4.0
2.0
0.8
0.4
Minimum execution time (s) Note: The shaded area is assured only for the MB89673/677A.
Figure 1
Operating Voltage vs. Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an minimum execution time of 4/FC. Since the operating voltage range is dependent on the minimum execution time, see minimum execution time if the operating speed is switched using a gear. 29
MB89670/A Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin
P00 to P07, P10 to P17, P30 to P37, P40 to P47
Condition
Value Min. 0.7 VCC Typ. Max.
VCC + 0.3
Unit
Remarks
P32 to P37,
VIH
"H" level input voltage
V
P44, and P47 are port input. P32 to P37, P44, and P47 are peripheral input. P32 to P37,
RST, MOD0, MOD1,
VIHS
P32 to P37, P44, P47, P60 to P67, P70 to P76
0.8 VCC
VCC + 0.3
V
VIL
"L" level input voltage
P00 to P07, P10 to P17, P30 to P37, P40 to P47
--
VSS - 0.3
0.3 VCC
V
P44, and P47 are port input. P32 to P37, P44, and P47 are peripheral input.
RST, MOD0, MOD1,
VILS
P32 to P37, P44, P47, P60 to P67, P70 to P76
VSS - 0.3
0.2 VCC
V
Open-drain output pin application voltage
VD
P80 to P85
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P71, P72, P74, P75 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P76
VSS - 0.3
VSS + 6.0
V
"H" level output voltage
VOH
IOH = -2.0 mA
4.0
V
VOL1
"L" level output voltage
IOL = 4.0 mA
--
--
0.4
V
VOL2 VOL3
P80 to P85 RST
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
IOL = 10 mA IOL = 4.0 mA
0.5 0.4
V V
Input leakage current (Hi-z output leakage current)
ILI1
P40 to P47, P50 to P57, P60 to P67, P70 to P76, MOD0, MOD1
0.0 V < VI < VCC
--
--
5
A
Without pullup resistor
ILI2
P80 to P85
P00 to P07, P10 to P17, P30 to P37, P40 to P47, P60 to P67, P70 to P76, RST
0.0 V < VI < VCC
--
--
1 100
A k
With pull-up resistor
Pull-up resistance
RPULL
VI = 0.0 V
25
50
(Continued)
30
MB89670/A Series
(Continued)
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin
Condition FC = 10 MHz VCC = 5.0 V tinst*2 = 0.4 s FC = 10 MHz VCC = 3.0 V tinst*2 = 6.4 s
Value Min. -- Typ. 12 Max. 20
Unit
Remarks
ICC1
mA
MB89673
ICC2
-- -- --
1 1.5 3
2 2.5 7
mA mA mA
MB89677A MB89PV670A MB89P677A
Sleep mode
ICCS1 Power supply current*1
VCC
FC = 10 MHz VCC = 5.0 V tinst = 0.4 s
*2
FC = 10 MHz VCC = 3.0 V tinst = 6.4 s
*2
ICCS2
--
1
1.5
mA
ICCH
VCC = 3.0 V TA = +25C Stop mode
FC = 10 MHz When A/D converter starts
--
--
1
mA
IA AVCC IAH
--
6
8
mA
FC = 10 MHz TA = +25C When A/D converter stops
--
--
1
A
Input capacitance CIN
Other than AVCC, AVSS, VCC, and VSS
f = 1 MHz
--
10
--
pF
*1: The measurement conditions of the power supply current are as follows: the external clock and open output pins. *2: For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics."
31
MB89670/A Series
4. AC Characteristics
(1) Reset Timing
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter RST "L" pulse width
Symbol tZLZH
Condition --
Value Min. 48 tHCYL Max. --
Unit ns
Remarks
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Condition --
Value Min. -- 1 Max. 50 --
Unit ms ms
Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
32
MB89670/A Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time
Symbol FC tXCYL PWH PWL tCR tCF
Pin X0, X1 X0, X1 X0 X0
Condition
Value Min. 1 100 Max. 10 1000 -- 10
Unit MHz ns ns ns
Remarks
--
20 --
External clock External clock
X0 and X1 Timing and Conditions
tXCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL
Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0 FC
X1
X0
X1 Open
C1
C2
(4) Instruction Cycle Parameter Symbol Value (typical) 4/FC, 8/FC, 16/FC, 64/FC Unit s Remarks (4/FC) tinst = 0.4 s when operating at FC = 10 MHz
Instruction cycle tinst (minimum execution time)
33
MB89670/A Series
(5) Recommended Resonator Manufacturers Sample Application of Piezoelectric Resonator (FAR series)
X0
X1 FAR*
C1
C2 *: Fujitsu Acoustic Resonator C1 = C2 = 20 pF8 pF (built-in FAR)
FAR part number (built-in capacitor type) FAR-C4CB-08000-M02 FAR-C4CB-10000-M02 Inquiry: FUJITSU LIMITED
Frequency 8.00 MHz 10.00 MHz
Initial deviation of FAR frequency (TA = +25C) 0.5% 0.5%
Temperature characteristics of FAR frequency (TA = -20C to +60C) 0.5% 0.5%
34
MB89670/A Series
Sample Application of Ceramic Resonator
X0
X1
*
C1
C2
Resonator manufacturer* Kyocera Corporation Murata Mfg. Co., Ltd.
Resonator KBR-7.68MWS KBR-8.0MWS CSA8.00MTZ
Frequency 7.68 MHz 8.0 MHz 8.0 MHz
C1 (pF) 33 33 30
C2 (pF) 33 33 30
R (k) -- -- --
Inquiry: Kyocera Corporation * AVX Corporation North American Sales Headquarters: TEL 1-803-448-9411 * AVX Limited European Sales Headquarters: TEL 44-1252-770000 * AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 852-363-3303 Murata Mfg. Co., Ltd. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
35
MB89670/A Series
(6) Clock Output Timing
(AVCC = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Cycle time CLK CLK
Symbol tCYC tCHCL
Pin CLK CLK
Condition --
Value Min. 1/2 tinst*
1/4 tinst - 0.07
Max. -- 1/4 tinst
Unit s s
Remarks
* : For information on tinst, see "(4) Instruction Cycle."
tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V
36
MB89670/A Series
(7) Bus Read Timing
(AVCC = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Valid address RD time RD pulse width Valid address Data read time RD Data hold time RD ALE time RD CLK time CLK RD time RD BUFC time BUFC Valid address time
Symbol tAVRL tRLRH tAVDV
Pin
RD, A15 to 08, AD7 to 0
Condition
Value Min.
1/4 tinst* - 0.06 1/2 tinst *- 0.02
Max. -- -- 1/2 tinst *
1/2 tinst *- 0.08
Unit s s s s ns s s s ns ns ns
Remarks
RD AD7 to 0, A15 to 08
RD, AD7 to 0 AD7 to 0, RD
-- -- 0 --
1/4 tinst* - 0.04 1/4 tinst* - 0.04 1/4 tinst* - 0.04
Wait No wait
RD Data read time tRLDV tRHDX tRHLH tRLCH tCLRH tRLBL tBHAV
-- -- -- -- -- -- --
RD, ALE
RD, A15 to 08
RD Address loss time tRHAX
RD, CLK RD, CLK RD, BUFC A15 to 08, AD7 to 0, BUFC
0 -5 5
* : For information on tinst, see "(4) Instruction Cycle."
CLK
2.4 V 0.8 V
tRHLH ALE 0.8 V
AD
2.4 V 0.8 V tAVDV 2.4 V
0.7 VCC 0.3 VCC
0.7 VCC 0.3 VCC tRHDX
2.4 V 0.8 V
A 0.8 V tAVRL
tRLCH tRLDV tRLRH
2.4 V tCLRH 0.8 V tRHAX
2.4 V 0.8 V
RD 0.8 V tRLBL
2.4 V tBHAV 2.4 V
BUFC 0.8 V
37
MB89670/A Series
(8) Bus Write Timing
(AVCC = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Valid address ALE time ALE time Address loss time
Valid address WR time
Symbol tAVLL tLLAX tAVWL tWLWH tDVWL tWHAX tWHDX tWHLH tWLCH tCLWH tLHLL tLLCH
Pin
AD7 to 0, ALE, A15 to 08 AD7 to 0, ALE, A15 to 08
Condition
Value Min.
1/4 tinst* 2 - 0.064
Max. -- -- -- -- -- -- -- -- -- -- -- --
Unit s ns s s ns s s s s ns s s
Remarks
5*1
1/4 tinst* 2 - 0.06 1/2 tinst* 2 - 0.02 1/2 tinst* 2 - 0.06
WR, ALE WR
AD7 to 0, WR WR, A15 to 08 AD7 to 0, WR
WR pulse width
Writing data WR time WR Address loss time WR Data hold time
--
1/4 tinst - 0.04 1/4 tinst - 0.04 1/4 tinst* - 0.04 1/4 tinst* 2 - 0.04
*2
*2
WR ALE time WR CLK time CLK WR time ALE pulse width ALE CLK time
WR, ALE WR, CLK WR, CLK ALE ALE, CLK
0
1/4 tinst - 0.035 1/4 tinst* 2 - 0.03
*2
*1: These characteristics are also applicable to the bus read timing. *2: For information on tinst, see "(4) Instruction Cycle."
CLK tLHLL 2.4 V ALE 0.8 V tAVLL 2.4 V 2.4 V AD 0.8 V 0.8 V 0.8 V tLLAX 2.4 V tLLCH
2.4 V 0.8 V tWHLH 0.8 V
2.4 V 0.8 V tWHDX 2.4 V tCLWH 0.8 V tWHAX tWLWH
tDVWH 2.4 V A 0.8 V tAVWL tWLCH
WR 0.8 V
2.4 V
38
MB89670/A Series
(9) Ready Input Timing
(AVCC = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter RDY valid CLK time CLK RDY invalid time
Symbol tYVCH tCHYX
Pin RDY, CLK
Condition
Value Min. 60 Max. -- --
Unit ns ns
Remarks * *
-- RDY, CLK 0
* : These characteristics are also applicable to the read cycle.
CLK
2.4 V
2.4 V
ALE
AD
Address
Data
A
WR tYVCH tCHYX
RDY tYVCH tCHYX Note: The bus cycle is also extended in the read cycle in the same manner.
39
MB89670/A Series
(10) Serial I/O Timing
(VCC = +5.0 V10%, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK valid SI hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK SCK, SO SI, SCK SCK, SI
Condition
Value Min. 2 tinst* -200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* Max. -- 200 -- -- -- -- 200 -- --
Unit s ns s s s s ns s s
Remarks
Internal shift clock mode
External shift clock mode
0 1/2 tinst* 1/2 tinst*
* : For information on tinst, see "(4) Instruction Cycle." Internal Shift Clock Mode
SCK 2.4 V 0.8 V 0.8 V tSCYC
tSLOV 2.4 V SO 0.8 V
tIVSH 0.8 VCC SI 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
External Shift Clock Mode
SCK 0.2 VCC
tSLSH
0.2 VCC
tSLOV 2.4 V SO 0.8 V
tIVSH 0.8 VCC SI 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
40
MB89670/A Series
(11) Peripheral Input Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Peripheral input "H" pulse width 1 Peripheral input "L" pulse width 1 Peripheral input "H" pulse width 2 Peripheral input "L" pulse width 2 Peripheral input "H" pulse width 3 Peripheral input "L" pulse width 3 Peripheral input "H" pulse width 3 Peripheral input "L" pulse width 3
Symbol tILIH1 tIHIL1 tILIH2 tIHIL2 tILIH3 tIHIL3 tILIH3 tIHIL3 TCI TCI
Pin
Condition
Value Min. 1 tinst* 1 tinst* Max. -- -- -- -- -- -- -- --
Unit s s s s s s s s
Remarks
EC, INT0 to INT7 EC, INT0 to INT7 ADST ADST ADST ADST
--
2 tinst* 2 tinst*
A/D mode Sense mode
64 tinst* 64 tinst* 64 tinst* 64 tinst*
* : For information on tinst, see "(4) Instruction Cycle."
tIHIL1
tILIH1
TCI 0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC
tIHIL2
tILIH2
EC INT0 to INT7
0.8 VCC 0.2 VCC 0.2 VCC
0.8 VCC
tIHIL3
tILIH3
ADST 0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC
41
MB89670/A Series
(12) Up/down Counter Input Timing
(AVCC = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter AIN input "1" pulse width AIN input "0" pulse width BIN input "1" pulse width BIN input "0" pulse width AIN BIN time BIN AIN time AIN BIN time BIN AIN time BIN AIN time AIN BIN time BIN AIN time AIN BIN time ZIN input "1" pulse width ZIN input "0" pulse width
Symbol tAHL tALL tBHL tBLL tAUBU tBUAD tADBD tBDAU tBUAU tAUBD tBDAD tADBU tZHL tZLL
Pin
Condition
Value Min. 2 tinst* 2 tinst* 2 tinst* 2 tinst* 1 tinst* 1 tinst* Max. -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit s s s s s s s s s s s s s s
Remarks
P36, P37, P33, P34 --
1 tinst* 1 tinst* 1 tinst* 1 tinst* 1 tinst* 1 tinst* 1 tinst* 1 tinst*
P32, P35
* : For information on tinst, see "(4) Instruction Cycle."
42
MB89670/A Series
tAHL
tALL
AIN
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC tBDAU
tAUBU
tBUAD 0.8 VCC
tADBD 0.8 VCC
BIN tBHL
0.2 VCC tBLL
0.2 VCC
tBHL
tBLL
0.8 VCC BIN
0.8 VCC 0.2 VCC 0.2 VCC tADBU
0.8 VCC
tBUAU
tAUBD 0.8 VCC
tBDAD 0.8 VCC
AIN tAHL
0.2 VCC tALL
0.2 VCC
0.8 VCC
0.8 VCC
tZHL ZIN tZLL 0.2 VCC 0.2 VCC
43
MB89670/A Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 10 MHz, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Resolution Linearity error
Differential linearity error
Symbol
Pin
Value Min. -- -- -- -- Typ. -- -- -- --
AVSS + 0.5 LSB AVR - 1.5 LSB
Max. 10 2.0 1.5 3.0
AVSS + 2.5 LSB AVR + 0.5 LSB
Unit bit LSB LSB LSB mV mV LSB s A V V A
Remarks
--
--
Total error
Zero transition voltage
VOT VFST
AN0 to AN7 AN0 to AN7
AVSS - 1.5 LSB AVR - 3.5 LSB
AVCC = AVR = VCC
Full-scale transition voltage
Interchannel disparity A/D mode conversion time
Analog port input current
-- -- IAIN -- IR --
AN0 to AN7 AN0 to AN7
-- -- -- -- -- 200
4 13.2 10 AVR AVCC
-- -- 0 0 --
At 10-MHz oscillation
Analog input voltage Reference voltage Reference voltage supply current
AVR AVR
AVR = 5.0 V
Precautions: * The smaller | AVR - AVSS |, the greater the error would become relatively. * The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 k If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 6 s at 10 MHz oscillation). An analog input equivalent circuit is shown below.
Sample hold circuit R 10 k is recommended. AN . C = 60 pF . . R =. 3 k ( If R > 10 k, it is recommended to connect an external capacitor of approx. 0.1 F. ) Analog channel selector Close for approx. 15 instruction cycles after activating A/D conversion. Microcontroller's internal circuit Comparator
Since the A/D converter contains sample hold circuit, the level of the analog input pin might not stabilize within the sampling period after A/D activation, resulting in inaccurate A/D conversion values, if the input impedance to the analog pin is too high. Be sure to maintain an appropriate input impedance to the analog pin. It is recommended to keep the input impedance to the analog pin not exceed 10 k. If it exceeds 10 k, it is recommended to connect a capacitor of approx. 0.1 F for the analog input pin. Except for the sampling period after A/D activation, the input leakage current of the analog input pin is less than 10 A. 44
MB89670/A Series
(1) A/D Converter Glossary * Resolution Analog changes that are identifiable with the A/D converter. * Linearity error The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1111" "11 1111 1110") from actual conversion characteristics * Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error The difference between theoretical and actual conversion values, caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise.
Theoreticall I/O characteristics 3FF 3FE 3FD Digital output 1.5 LSB Digital output VFST 3FF 3FE 3FD
Total error
Actual conversion value {1 LSB x N + 0.5 LSB}
004 003 002 001 0.5 LSB AVSS Analog input AVR
004 VNT 003 Actual conversion value Theoretical value 001
VOT 1 LSB
002
AVSS Analog input
AVR
1 LSB =
VFST - VOT 1022
(V)
Total error of digital output N
VNT - {1 LSB x N + 0.5 LSB} 1 LSB
(Continued)
45
MB89670/A Series
(Continued)
Zero transition error 004 Actual conversion value 003 Digital output Digital output 3FE 3FF
Full-scale transition error Theoretical value
Actual conversion value
002 Theoretical value 001
VFST (Actual measured value) 3FD Actual conversion value 3FC
Actual conversion value
VOT (Actual measured value) AVSS Analog input Analog input AVR
Linearity error 3FF 3FE {1 LSB x N + VOT} 3FD Digital output Digital output VFST (Actual measured VNT value) 004 003 002 001 VOT (Actual measured value) AVSS Analog input AVR AVSS Actual conversion value Theoretical value N-2 N Actual conversion value N+1
Differential linearity error Theoretical value
Actual conversion value
V(N + 1)T
N-1
VNT Actual conversion value
AVR Analog input
Linearity error of digital output N =
VNT - {1 LSB x N + VOT} 1 LSB
Differential linearity error of digital output N =
V(N+1)T - VNT 1 LSB
-1
46
MB89670/A Series
s EXAMPLE CHARACTERISTICS
(1) "L" Level Output Voltage (2) "H" Level Output Voltage
VOL (V) TA = +25C 0.5
VOL vs. IOL
VCC = 2.5 V
VCC - VOH (V) 1.0 TA = +25C 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0
VCC - VOH vs. IOH
VCC = 2.5 V
VCC = 3.0 V 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0 IOH (mA)
(3) "H" Level Input Voltage/"L" Level Input Voltage (CMOS Input)
(4) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
VIN vs. VCC
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 VCC (V)
VIN vs. VCC
TA = +25C
VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5
TA = +25C VIHS
VILS
6
7 VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
47
MB89670/A Series
(5) Power Supply Current (External Clock)
ICC (mA) 25
ICC1 vs. VCC, ICC2 vs. VCC
ICCS1 vs. VCC, ICCS2 vs. VCC
ICCS (mA) 25 TA = +25C FC = 10 MHz External clock 20
20
TA = +25C FC = 10 MHz External clock
ICC1 (Divide by 4)
15
15
10
10 ICCS1 (Divide by 4)
5
ICC2 (Divide by 64)
5
ICCS2 (Divide by 64)
0 2 3 4 5 6 7 VCC (V)
0 2 3 4 5 6 7 VCC (V)
(6) Pull-up Resistance
RPULL vs. VCC
RPULL (k) 1000 500 TA = +25C
100 50
10 1 2 3 4 5 6 VCC (V)
48
MB89670/A Series
s INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning
(Continued)
49
MB89670/A Series
(Continued)
Symbol EP PC SP PS dr CCR RP Ri x (x) (( x )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
50
MB89670/A Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
51
MB89670/A Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
52
MB89670/A Series
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
53
54
3 RETI SETC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP
PUSHW POPW MOV MOVW CLRI A A A,ext A,PS
L SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC
H 4 5 6 7 8 9 A B C D E F
0
1
2
0
NOP
SWAP
RET
1 SUBC A A
MULU
DIVU
A XCH XOR AND OR A, T A A
A
PUSHW POPW MOV MOVW CLRC JMP CALL IX IX ext,A PS,A addr16 addr16
2
ROLC
CMP
ADDC
A
A
A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
s INSTRUCTION MAP
3 XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS
RORC
A
MOVW MOVW CLRB BBC INCW DECW MOVW MOVW CMPW ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP A CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
MB89670/A Series
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
SUBC A,@IX +d
@IX +d,#d8 @IX +d,#d8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP
MOV @IX +d,A MOV @EP ,#d8 @EP ,#d8 CMP A,@IX +d A,@IX +d A,@IX +d XOR AND OR
6
MOV
CMP
ADDC
MOV
CMP
MOVW A,@IX +d
MOVW @IX +d,A
A,@IX +d
A,@IX +d
A,@IX +d
CLRB BBC dir: 6 dir: 6,rel
MOVW XCHW IX,#d16 A,IX
7
MOV CMP ADDC SUBC MOV XOR AND OR A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP
CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP EP ,A ,#d16 A,EP
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel rel rel rel
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel
F
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel
MB89670/A Series
s MASK OPTIONS
Part number No. Specifying procedure Pull-up resistors P10 to P17, P30 to P37, P40 to P47, P70 to P76 Pull-up resistors P00 to P03 Pull-up resistors P04 to P07 Power-on reset With power-on reset Without power-on reset Oscillation stabilization time selection (at 10 MHz)
Approx. 218/FC (about 26.2 ms)
MB89673 MB89677A Specify when ordering masking Selectable by pin
MB89P677A Set with EPROM programmer Selectable by pin Selectable in 4-pin unit Selectable in 4-pin unit Selectable
MB89PV670A Setting not possible
1
2 3 4
Selectable by pin Selectable by pin Selectable
Fixed to without pull-up resistor
Fixed to with power-on reset
5
Approx. 217/FC (about 13.1 ms) Approx. 214/FC (about 1.6 ms) Approx. 24/FC (about 0 ms)
Selectable
Selectable
Fixed to Approx. 218/FC (Approx. 26.2 ms)
FC: Clock frequency 6 Reset pin output With reset output Without reset output Selectable Selectable Fixed to with reset output
s ORDERING INFORMATION
Part number MB89673PF MB89677APF MB89P677APF MB89673PFM MB89677APFM MB89P677APFM MB89P670ACF Package 80-pin Plastic QFP (FPT-80P-M06) 80-pin Plastic QFP (FPT-80P-M11) 80-pin Ceramic MQFP (MQP-80C-P01) Remarks
55
MB89670/A Series
s PACKAGE DIMENSIONS
80-pin Plastic QFP (FPT-80P-M11)
16.000.20(.630.008)SQ
60
14.000.10(.551.004)SQ
41
1.50 -0.10 +.008 .059 -.004
+0.20
61
40
12.35 15.00 (.486) (.591) REF NOM
1 PIN INDEX
80 21
LEAD No.
1 20
"A" 0.300.10 (.012.004) 0.13(.005)
M
Details of "A" part 0.127 .005
+0.05 -0.02 +.002 -.001
0.65(.0256)TYP
0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F80016S-1C-2
Dimensions in mm (inches)
56
MB89670/A Series
80-pin Plastic QFP (FPT-80P-M06)
23.900.40(.941.016)
64 65
20.000.20(.787.008)
41 40
3.35(.132)MAX 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
80 25
17.900.40 (.705.016)
12.00(.472) REF
16.300.40 (.642.016)
"A" LEAD No.
1 24
0.80(.0315)TYP
0.350.10 (.014.004)
0.16(.006)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX
Details of "B" part
0 10 0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F80010S-3C-2
Dimensions in mm (inches)
57
MB89670/A Series
80-pin Ceramic MQFP (MQP-80C-P01)
18.70(.736)TYP 12.00(.472)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.20 -0.20 +.016 .047 -.008
+0.40
INDEX AREA
0.800.25 (.0315.010) 0.800.25 (.0315.010)
1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP
INDEX AREA 18.40(.724) REF
INDEX 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.400.10 (.016.004) 1.50(.059) TYP 1.00(.040) TYP
1.270.13 (.050.005)
0.400.10 (.016.004)
1.20 -0.20 +.016 .047 -.008
+0.40
0.150.05 8.70(.343) (.006.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches)
58
MB89670/A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9602 (c) FUJITSU LIMITED Printed in Japan
59

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